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Pro-Form ZE5 Especificações Página 98

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Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 98
ZE505 4.5 6.0 ns
ZE512 4.5 6.0 ns
flop or latch using the Bus Clock Input as clock,
delayed input path.
ZE520 4.5 6.0 ns
Preliminary
G
G
l
l
o
o
b
b
a
a
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B
B
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f
f
f
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r
r
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O
O
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D
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y
OUTFF
Global
Buffer
GBUFx
PIO
35 pF12 mA
Figure 51. Global Buffer clock to Output from output flip-flop, 12 mA driver.
Speed Grade All -25 -40
Description Symbol Device Min [1] Max Max
Units
ZE505 2.0 23.0 17.0 ns
ZE505 2.0 23.0 17.0 ns
ZE512 2.0 23.0 17.0 ns
Global Buffer (GBUFx) pad to output delay
using output flip-flop.
T
GPCO
ZE520
2.0 23.0 17.0 ns
Preliminary
Note 1:
Not tested. Guaranteed by design.
B
B
u
u
s
s
C
C
l
l
o
o
c
c
k
k
I
I
n
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p
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u
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O
O
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E
E
n
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a
a
b
b
l
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D
D
e
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y
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OEFF
GBUFx
PIO
35 pF
12 mA
Global
Buffer
Figure 52. Bus Clock to Output from output flip-flop, 12 mA driver.
Speed Grade All -25 -40
Description Symbol Device Min [1] Max Max
Units
ZE502 2.0 18.0 13.5 ns
ZE505 2.0 18.0 13.5 ns
ZE512 2.0 18.0 13.5 ns
Bus Clock Input (BCLK/XTAL) pad to output
valid using output-enable flip-flop.
T
GPEO
ZE520
2.0 18.0 13.5 ns
ZE502 2.0 25.5 19.5 ns
ZE505 2.0 25.5 19.5 ns
ZE512 2.0 25.5 19.5 ns
Bus Clock Input (BCLK/XTAL) pad to output
high-impedance (hi-Z) using output-enable
flip-flop.
T
GPEZ
ZE520
2.0 25.5 19.5 ns
Preliminary
Note 1:
Not tested. Guaranteed by design.
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